1. Field of the Invention
The present invention relates to an interconnect system for electrical devices; more particularly, to a pressure activated package for housing semiconductor chips in a two-dimensional array and providing electrical interconnections between the chips.
2. Description of the Related Art
The time required for an electrical pulse to travel along a conductor from one active electrical device to another is one of the factors which determines the performance of an electronic package (or assembly). The factors which determine this time are (1) the physical distance between the devices and (2) the propagation velocity of the pulse. One parameter which affects the propagation velocity is the dielectric constant of the materials used to support the conductor. As an example and to provide a basis for comparison, the signal propagation velocity for conventional printed circuit boards is on the order of 50-60% of the speed of light (c).
In the prior art, each of the above issues has been addressed by utilizing increasingly complex multilayer printed wiring boards. To accommodate the device density requirements of system designers, via holes have become smaller and closer together, interstitial vias have been developed for selective connection of layers, conductor lines have become narrower and closer together, the number of conductive layers in the printed wiring boards has been increased, and alternative materials having reduced dielectric constants have been developed and utilized. Physical limits are being approached for each of the foregoing parameters, which create the need for improved packages and packaging technology.
Further, indigenous to printed wiring board technology is the dedicated routing of conductor paths in complex assemblies. Revisions to the routing for repair or re-design purposes are accomplished with great difficulty, usually involving the physical cutting of the conductor to be re-routed and connecting a wire to the new termination points.
Two different types of packages (or interconnect systems) have been used to provide connections between the various chips in a package, so-called "two-dimensional packages" and "three-dimensional packages." In a two-dimensional package, the package includes an interconnect structure having plural leads passing in the x, y and z directions within the interconnect structure for electrically interconnecting semiconductor chips provided on the exterior of the interconnect structure. Such a package usually comprises a plurality of wafers provided in a stack with x and y interconnects on the surface of or contained in the wafers and z interconnects passing through the wafers.
As used herein, the term "package(s)" refers to devices for housing and/or interconnecting plural electrical devices, particularly, semiconductor chips, and the alternative terms "chip(s)", "semiconductor chip(s)", and "semiconductor device(s)" refer to an encapsulated die having bonding pads provided thereon.
An example of a two-dimensional package is illustrated in U.S. Pat. No. 3,705,332. An example of a three-dimensional package is disclosed in U.S. Pat. No. 3,769,702. Other U.S. Patents pertaining to packages for semiconductor chips include U.S. Pat. No. 3,775,844; U.S. Pat. No. 3,813,773; U.S. Pat. No. 3,917,983; U.S. Pat. No. 4,268,956; and U.S. Pat. No. 4,283,754.
High-density multilayer printed wiring boards using through-hole technology for assembling electrical devices, and extra-high-density multilayers that are suitable for surface mounting of electrical devices have been developed to provide increasingly smaller spacings between devices and increasingly larger pin densities and counts per device. Each offers the following features: (1) Modularized packaging--electrical devices may be architecturally grouped according to function and located on one multilayer printed wiring board; (2) Mass assembly--printed wiring boards may be batch assembled and mass-soldered to achieve economic advantages; (3) Serviceability--repairs to large systems may be easily accomplished by removing and replacing modules which fail in service; and (4) Reliability--the in-service failure rate of multilayer printed wiring boards is significantly less than that of other components in the system.
The continuing trend toward greater integration of electrical devices on one interconnection mechanism, and the value of increased pulse propagation velocity have caused many features of conventional multilayer printed wiring boards to approach physical limits. For example, it is impractical to drill large quantities of high-aspect-ratio holes (holes having a large length-to-diameter ratio) less than approximately 0.011" in diameter; it is extremely difficult to metallize through-via holes having aspect ratios greater than approximately 8:1; it is extremely difficult to register and laminate greater than approximately 30 conductive layers; and it is extremely difficult to process low dielectric constant materials into high layer count multilayers. Each of the foregoing difficulties contributes significantly to the cost of the product. When two or more difficulties are faced in fabricating one part, the costs can escalate geometrically as the manufacturing yields approach zero.